FIG. 18A is a diagram illustrating a general configuration of high-speed serial transmission between LSIs in an information device typified by a computer or a network device. The configuration includes an output driver 1501 within a transmitter circuit, a transmission line 101, and an input circuit 104 within a receiver circuit, where the input circuit 104 outputs an output differential signal Vo corresponding to a differential signal Vin so that a logic level is determined according to a difference in an output level between Vop and Von. In the input circuit 104, an error is generated in a level difference between differential signals due to the variation in device characteristic, which can be represented by an equivalent circuit, as illustrated in FIG. 18B. That is, an error voltage Voff shifting a level of an input signal is applied to one of input signals. The error voltage Voff takes a positive or negative value according to a variation amount in circuit characteristic. The error voltage Voff is generally called “offset voltage” 1801. Because of an influence of the offset voltage, a positional relationship between Vop and Von is reversed, an erroneous operation occurs, and transmission quality lowers upon performing a signal transmission. As a general technique of realizing offset voltage reduction of an input circuit, there is a technique such as that described below.
For example, based on Patent Document 1 (U.S. Patent Application Publication No. 2006/0067440), FIG. 19 is a diagram illustrating a configuration example of an input circuit in which an output offset voltage in a signal receiver circuit with respect to a high-speed serial transmission between LSIs is suppressed to a low value. The configuration illustrated in FIG. 19 includes an input circuit 104, a clock and data recovery (CDR) 1901, and an offset voltage correcting circuit 1902. In the configuration, before a normal operation is performed, ten fixed patterns for offset voltage adjustment are transmitted, eye widths between cross points of differential waveforms are observed in the CDR 1901, and the eye widths are adjusted such that eye amplitudes in even number bit and odd number bit become equal to each other. Thereby, an output offset voltage in the input circuit 104 is reduced.
FIG. 20A is a diagram illustrating an output waveform of the input circuit 104 obtained when 10 fixed patterns are transmitted in the case of not having an offset voltage in the input circuit 104. When an offset voltage is not present in the input circuit 104, eye widths Te and To of an even number bit and an odd number bit are equal to each other, and eye amplitudes Ae and Ao of the even number bit and the odd number bit are equal to each other. As illustrated in FIG. 20B, for example, when a positive offset voltage is generated in the input circuit 104, eye widths Te′ and To′ of the even number bit and the odd number bit are different from each other, and eye amplitudes Ae′ and Ao′ of the even number bit and the odd number bit are different from each other, resulting in Te′<To′ and Ae′<Ao′. The input circuit illustrated in FIG. 19 supplies such a control signal that the eye widths Te′ and To′ become equal to each other at the clock and data recovery 1901 to the offset voltage correcting circuit 1902, and the offset voltage correcting circuit 1902 adjusts the input circuit 104 according to the control signal so that the eye amplitudes Ae′ and Ao′ become equal to each other, thereby reducing the offset voltage.